Texas Instruments LMK03328 ultra-low jitter clock generator includes two fractional-N frequency synthesizers with integrated VCO, flexible clock distribution / fan-out, and pin-selectable configuration states stored in on-chip EEPROM. The device can generate multiple clocks for a variety of gigabit serial interfaces and digital devices. This reduces BOM cost and board area, and improves reliability by replacing multiple oscillators and clock distribution equipment. Ultra-low jitter reduces the bit error rate (BER) in high-speed serial links.
For each PLL, a differential / single-ended clock or crystal input can be selected as the PLL reference clock. The selected PLL reference input can be used to lock the VCO frequency to an integer or fractional multiple of the reference input frequency. The VCO frequency of each PLL can be adjusted between 4.8GHz and 5.4GHz. Both PLLs / VCOs are equivalent in performance and functionality. Each PLL has the flexibility to choose a predefined or user-defined loop bandwidth based on application requirements. Each PLL has a postscaler that can be selected between 2, 3, 4, 5, 6, 7, or 8.
Applications include switches / routers, network / telecom line cards, servers / storage systems and wireless base stations.
