Portland, Oregon-Researchers sponsored by Semiconductor Research Corporation (SRC, Triangle Research Park, North Carolina) claim that they have found a way to reduce serial link power consumption by 80%, extending Moore's Law . The innovation at the University of Illinois (Urbana) is a new on / off transceiver that can be used in chips, between chips, between boards, and between data center servers.
The team estimates that the technology can reduce the power consumption of communications by up to 44 times and extend Moore's Law by adding computing power without increasing power consumption. "While the technology is not designed to make processors run faster, it does allow the power saved in the link budget to be used elsewhere in the context of the data center," said David Yeh, director of SRC integrated circuit and systems sciences. Tell EETimes.
Today, on-chip serial links consume about 20% of the microprocessor's power, while the data center's total power budget accounts for about 7%. By using a transceiver that consumes power only when in use, you can save a lot of power from its standby power consumption.
The reason the link is always online is to maximize speed. The new architecture reduces its power-up time, so it's worth turning it off when not in use. The team estimates that the data center alone could save $ 870 million annually by converting its transceiver architecture.
By using an on / off transceiver, the chip can reduce communication and signaling power consumption by 80%.
(Source: SRC)
One of the principal researchers, Professor Pavan Kumar Hanumolu, explained:
Due to the slow feedback loop used in clock generation and data recovery circuits, a typical link takes a long time (several microseconds) to synchronize the receiver with the transmitter. As a result, this kind of link takes a long time to open from a closed state (called the power-up time), so it cannot be opened and closed quickly. Such a long power-on time severely limits the power saving capabilities during idle links. New technology reduces link power-up time to 20 nanoseconds, saving power even during short idle times. For further quantification, the new link consumes 44 times less power than a typical link using 1% utilization.
To prove this concept, Hanumolu's team built what they consider to be the world's first on / off transceiver, which is fast enough to do the job, a 7 Gb per second model, and compared to a normally open model Has its performance. Other organizations have also tried to build transceivers, but Hanumolu believes that their power-up time is too slow-in the range of 100 nanoseconds-and of course energy-efficient Ethernet (IEEE 802.3az), but it takes microseconds. Turn on, and the University of Illinois design takes only 22 nanoseconds.
Of course, power savings depend on the application, and circuits that are always on (such as a clock) will not be appropriate. However, according to Hanumolu, serial connections between the chip and the system and between the chip and the system are few, but very necessary, so the average transceiver consumes 10 times less power than traditional transceivers .
"The electrical link we are talking about may or may not be a separate chip, or it may be integrated," Hanumolu said. "Almost all link circuits-the entire transceiver-are on and off. In other words, the transceiver The device is only turned on during data transfer and is turned off when it is idle (the power consumption is almost zero). Active and idle time depends on the application, "he said
Researchers estimate that the average idle time of serial links exceeds 50% to 70%, which wastes a lot of power and keeps them idle at all times. Even mobile platforms can benefit from smart on / off transceivers, especially when they become a standard part of the system-on-chip (SoC) architecture. Researchers claim that their on / off transceivers can be implemented on any technology node and are equally applicable to memory and communication links.
SRC members who can use this technology for free include GlobalFoundries, IBM, Intel, Freescale, Texas Instruments, Advanced Micro Devices, Analog Devices and Qualcomm. Funding was provided by the Texas Analog Center of Excellence, SRC, and the University of Illinois.
