LVDS SerDes transmitter and receiver | Heisener Electronics
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LVDS SerDes transmitter and receiver

Technology Cover
Post-datum: 2023-04-12, CEL

The THCV213 and THCV214 are designed to support the transfer of pixel data between the host and the display. The chipset is only capable of transmitting 18 bits of data and 4 bits of control data via a differential cable, with a pixel clock frequency from 5MHz to 40MHz. With V-by-One® technology, a unique coding scheme and proprietary CDR technology, link synchronization is achieved without any external frequency reference, such as a crystal oscillator. It greatly increases the cost and space of display system pcb.


Pin Configuration

                    

The THCV213 transmitter converts input data into a single LVDS serial data stream with an embedded clock. It supports pre-emphasis for long cable transmission. The THCV214 receiver extracts the clock from the embedded clock and converts the serial data stream back to parallel data.


To verify link reliability, the following functions are supported. THCV213 can transmit synchronous mode to speed up the establishment of links. The THCV214 has a PLL status indicator.


Block Diagram

               


Features

● Transfer 18 bits of data and 4 bits of control data single differential cable

● Wide frequency range :5MHz ~ 40MHz

● SYNC mode and LOCK indicator are supported

● Preemphasis mode

● Clock edge Optional

● Dual display mode

● Power off mode

● Low power single chip 3.3V CMOS design

● 48pin TQFP

● AEC-Q100 ESD protection


Packet information

                     

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