The Teledyne E2V offers the EV12AQ600/5 model with an integrated license key that provides direct access to the new ADX4 post-processing algorithm created by SP devices within the Teledyne Group. Spur Reduction IP Dynamic attenuation of spurious frequency components caused by gain, offset, and phase mismatches between four ADC cores. Time interleaving is a trusted architecture method to improve ADC sampling rate. However, calibration to avoid concomitant spectral artifacts is particularly challenging in resolution and broadband applications above 10 bits.
The time-staggered four-core sampling rate is increased from 1.6gs /s to 6.4gs /s by a factor of four. The mismatch error between ADC cores reduces the pseudo-free performance. The ADX4 produces pseudo-free dynamic range gain of up to 10dB. This improvement is particularly evident in broadband applications, where no hardware design changes are required and therefore can be provided on demand. The ADX4 coding module is programmed into post-processing FPGA. It can even be modified in the field.
Through the desired supply chain, customers only need to transfer their orders to the -ADX4 option of their equipment. Also, they need to add the module to the Xilinx FPGA code load. Getting the ADX4 Dynamic Boost couldn't be easier.
