Cypress introduced what it considers to be the industry's highest density synchronous SRAM with on-chip error correction codes (ECC). The integrated ECC function enables the new 36Mb synchronous SRAM to provide the highest level of data reliability, thereby simplifying the design for various military, communications and data processing applications. Cypress plans to expand the high-performance synchronous SRAM series with ECC at a higher density later this year.
Soft errors caused by background radiation may destroy memory contents, resulting in the loss of critical data. The hardware ECC block in Cypress's new synchronous SRAM can perform all error correction functions online without user intervention, and can provide first-class soft error rate (SER) performance. Synchronous SRAM with ECC is pin compatible with current synchronous SRAM, allowing customers to enhance SER and system reliability while maintaining circuit board layout. In addition, the new SRAM helps reduce power consumption by up to 36% compared to competitor solutions.
"Cypress is the global market leader in synchronous SRAM. This new device family with on-chip ECC demonstrates our commitment to expanding our standard synchronization, NoBL and QDR SRAM product portfolio," said Oliver Pohland, director of the synchronous SRAM business unit Cypress. "Like our entire SRAM product portfolio, these new devices are supported by Cypress's best-in-class manufacturing and customer support." The
new 36Mb synchronous SRAM is currently available in RoHS-compliant 100-pin TQFP and 165-ball BGA packages for industrial use Temperature class.
