Flex Logix, Inc., a leading provider of reconfigurable computing solutions, architecture and software, and CEVA, Inc. (NASDAQ: CEVA, Inc., a global licensor of wireless connectivity and smart sensing technologies and integrated IP solutions) : CEVA) announced the successful launch of the world's first integrated CEVA-X2 DSP instruction extension interface Flex Logix EFLX embedded FPGA (eFPGA) chip product. Called SOC2, the ASIC device supports a flexible and changeable instruction set to meet demanding and changing processing workloads. The product was designed by the SoC Lab at Bar-Ilan University and taped out using TSMC's 16 nm technology. The SoC Lab at Bar-Ilan University is part of the HiPer Alliance and is supported by the Israel Innovation Authority (IIA).
"Adding custom instructions to minimize power consumption and maximize performance efficiency in embedded processors has been the most effective approach for decades," said Andy Jaros, vice president of eFPGA IP sales and marketing at Flex Logix. Suitable for specific industry applications, however when applications change or new use cases require different instructions, developing new chips can be expensive The Set Architecture (ISA) approach enables customization of instructions to meet different application scenarios, and users can change these customized instructions at any time in the future."
Erez Bar-Niv, CEVA CTO, said: "As a member of the HiPer Alliance, we are delighted to be working with the Bar-Ilan University SoC Labs team and Flex Logix to test new capabilities of the CEVA-X2 DSP that have not been tried before. SOC2 consists of two Processing clusters, each containing two CEVA-X2 DSP cores and an EFLX eFPGA for programming and executing DSP instruction extensions, connected using the CEVA-Xtend mechanism. Now, joint customers of Flex Logix and CEVA can ISA post-manufacturing to target top-level DSP applications in different communications and audio domains, confidently using custom instructions to fully capture the value of ASICs.”
EFLX eFPGAs can be used anywhere in the ASIC architecture. In addition to the ISA extension interface, EFLX is used for packet processing, security, encryption, IO multiplexers, and general algorithm acceleration. Using EFLX, chip developers can implement eFPGAs ranging from a few thousand LUTs to over a million LUTs with performance and density per square millimeter comparable to those of leading FPGA companies of the same generation. The EFLX eFPGA is modular, so its array can be distributed throughout the chip, making it suitable for all-logic or heavy-DSP, and it can integrate RAM. EFLX eFPGA now supports 12, 16, 22, 28, and 40 nm process nodes, and is developing 7 nm process node applications, with plans to release more advanced node products in the future.
CEVA-X2 is based on a multi-purpose hybrid DSP and controller product with 10-stage pipeline and 5-way VLIW/SIMD architecture, which can run at over 1GHz in 16nm process. As an advanced DSP optimized for intensive workloads, it is specifically designed to handle use cases such as 5G PHY control, multi-microphone beamforming, artificial intelligence processing, and neural network implementation. The CEVA-X2 supports various software needs using the extensive CEVA DSP library, CEVA Neural Network library, and software solution offerings for various applications from a large ecosystem of partners.
