The XRD98L23 is a complete linear CIS or CCD sensor signal processor on a single chip. It includes a high-speed 8-bit resolution ADC, a 6-bit programmable gain amplifier with gain adjustment 1 to 10, and a typical 8-bit programmable input reference bias calibration range of 480mV.
In a CCD configuration, the input signal is AC, plus an external capacitor. Internal tongs set black level. In the CIS configuration, the clamp switch can be disabled and the CIS output signal is coupled from the CIS sensor to XRD98L23. CIS signal level is transferred to VRB in order to use the full range of ADC.
In a CIS configuration, the input can also be AC coupled similar to a CCD configuration. This causes CIS signals with large black levels to be internally clamped to a DC reference equal to the black level. The DC reference is subtracted from inside the input signal. CIS configuration can also be used for other applications that do not require CDS capabilities, such as low-cost data acquisition.
XRD98L23 Pin arrangement
XRD98L23 Functional Block Diagram
Working principle
There are two CIS application configurations for XRD98L23. Each configuration is set by a control register accessed through the serial port.
DC Coupled
If the CIS has no front or back black pixels, as shown in the figure below, then the DC coupled CIS outputs to the XRD98L23 input.
Typical output CIS pattern
Adjust the offset of CIS (-60 mV to 300 mV) by setting the internal register of XRD98L23 to set the black pixel value of CIS when its led is off. When the led lights up, the XRD98L23 programmable gain is used to maximize the dynamic range of the adc. The following figure shows a typical application of CIS with offsets of -60mV to 300mV.
The offset ranges from -60mv to 300mv
Input is added to the VRB before the signal passes through the ADC. If the CIS output is zero, then the ADC output will be zero code. This allows CIS to be referenced to the underlying ladder reference voltage to use the full range of the ADC. Some CIS sensors have output bias voltages greater than 300mV.
If the CIS output is outside the bias range of XRD98L23 (see Bias Control DAC, page 27), set the internal mode register to the external reference. To satisfy the dynamic range of XRD98L23, an external reference voltage equal to the CIS offset voltage value can be applied to vdext(shown below). This figure is a schematic of the XRD98L23 external reference mode for CIS, DC coupled applications.
Application with Offset Greater Than (-60mv to 300mv)
The DC reference voltage applied to vdext does not need to be precise. The internal biased DAC voltage is still used for fine tuning in this mode. vdext cannot be used as input from CIS. Any signal applied to the vdext will be subtracted from the output signal of the multiplexer.
Typical application circuit CIS DC coupled non-reverse mode with VDC external bias compensation
Features
● 8 bit resolution, no leakage code
● Single channel 10MSPS pixel rate
● Dual channel 5MSPS pixel rate
● Three-channel 3 MSPS pixel rate
● 6-bit programmable gain amplifier
● 8-bit programmable offset adjustment
● CIS or CCD compatible
● CIS or CCD AC coupled clip configuration
● 3.3V operation and I/O compatibility
● Serial load control register
● Low power CMOS: 75mw type
● Low cost 20 lead pack
● USB compatibility
Applications
● Inspection scanner
● Universal CIS or CCD imaging
● Low cost data acquisition
● Simple and direct interface Canon 600 DPI sensor
